Signal timing is a critical aspect of high-speed digital circuit design. Reading data from memory and writing data to memory can be erroneous if control signals are not in sync with each other. In high frequency digital design, control signals can go out of sync due to different length of tracks they traverse on PCB, physical characteristics of the devices mounted on the board and changes in environment in which circuit is working.
In “Scheme for Optimal Settings for DDR Interface”, U.S. application for patent application Ser. No. 60/485,597 , by Kumar, et al., there is described a scheme for arriving at optimal settings for a DDR interface, based on the acquisition of statistical data to define an operating region. However, it is possible in some cases, that the NDCL offset can be quite large. If the printed circuit board skew is large enough to make the offset large, and the foregoing is not compensated, voltage and temperature changes can cause drifting away from the optimal operating point.
Additionally, if the NCDL has a large number of taps, it would increase the run-time of the algorithm. Additionally, for a Fast/Fast (FF) process with high voltage and low temperature, more NCDL taps will pass, while for a Slow/Slow (SS) process with low voltage and high temperature, fewer NCDL taps will pass.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the inventions as set forth in the remainder of the present application with reference to the drawings.